1. Field of the Invention
The present invention relates to a semiconductor device with a multi-layered wiring arrangement including reinforcing metal patterns formed therein, and a production method for manufacturing such a semiconductor device.
2. Description of the Related Art
In a representative process of producing a plurality of semiconductor devices, for example, a silicon wafer is prepared, and a surface of the silicon wafer is sectioned into a plurality of semiconductor chip areas by forming grid-like fine grooves (i.e. scribe lines) in the silicon wafer. Then, the silicon wafer is processed by various well-known methods such that various elements, such transistors, resistors, capacitors and so on, are produced in each of the semiconductor chip areas on the silicon wafer, and an insulating layer, such as a silicon dioxide layer, is formed as an underlayer on the silicon wafer. Also, a plurality of contact plugs, made of a suitable metal material, are formed in an area of the insulating underlayer, which corresponds to each of the semiconductor chip areas, and each of the contact plugs is electrically connected to an element produced in the corresponding semiconductor chip areas.
Subsequently, a multi-layered wiring arrangement is constructed on the insulating underlayer of the silicon wafer, using various processes, for example, a chemical vapor deposition (CVD) process, a photolithography process, an etching process, a sputtering process, an electroplating process, and so on.
The multi-layered wiring arrangement includes at least three insulating interlayer structures: a lowermost insulating interlayer structure formed on the insulating underlayer of the silicon wafer and having respective metal wiring layout patterns formed thereon for the semiconductor chip areas on the silicon wafer; at least one intermediate insulating interlayer structure formed on the lowermost interlayer structure and having respective metal wiring layout patterns formed thereon for the semiconductor chip areas on the silicon wafer; and an uppermost insulating interlayer structure formed on the intermediate insulating interlayer structure and having respective plural sets of electrode pads formed thereon for the semiconductor chip areas on the silicon wafer. Further, the multi-layered wiring arrangement includes a passivation layer as a protective layer, which is formed on the uppermost insulating interlayer structure, and which is perforated such that the electrode pads are exposed to the outside.
Each of the metal wiring layout patterns included in the lowermost insulating interlayer structure is suitably and electrically connected to the contact plugs provided for a corresponding semiconductor chip area through the intermediary of via plugs formed in the lowermost insulating interlayer structure. Also, each of the metal wiring layout patterns included in the intermediate insulating interlayer structure is suitably and electrically connected to a corresponding metal wiring layout pattern, included in the lowermost insulating layer structure, through the intermediary of via plugs formed in the intermediate insulating interlayer structure. Further, each set of electrode pads included in the uppermost insulating interlayer structure are suitably and electrically connected to a corresponding set of metal wiring layout patterns included in the insulating interlayer structure, through the intermediary of via plugs formed in the uppermost insulating interlayer structure.
After the construction of the multi-layered wiring arrangement, the silicon wafer is subjected to a dicing process, in which the silicon wafer is cut along the grid-like grooves, whereby the semiconductor chip areas are separated from each other as semiconductor devices (bare chips).
Each of the aforesaid insulating interlayer structures is frequently constituted by some insulating layers, which are respectively made of different insulating materials. For example, as shown in JP-A-2001-168093, the insulating interlayer structure is constituted by a silicon nitride (SiN) layer, a spin-on-glass (SOG) layer formed thereon, and a silicon dioxide (SiO2) layer formed thereon. Since the SOG layer exhibits an inferior adhesion property with respect to both the SiN layer and the SiO2 layer, the SiN layer and the SiO2 layer are liable to be peeled from the SOG layer when being repeatedly subjected to thermal stresses.
Therefore, in JP-A-2001-168093, it has been proposed that reinforcing metal patterns, called dummy wiring patterns, are incorporated in the multi-layered wiring arrangement. In particular, two sets of reinforcing patterns are formed on two adjacent insulating interlayer structures of the multi-layered wiring arrangement, and are connected to each other through the intermediary of via plugs formed in the upper one of the two adjacent insulating interlayer structures, whereby the peeling of the SiN and SiO2 layers from the SOG layer can be prevented.
Each of the aforesaid semiconductor devices (bare chips) is used to manufacture a molded-resin semiconductor package. In this case, as well known, the semiconductor device is subjected to a wire-bonding process in which a gold wire is bonded and connected to each of the electrode pads on the semiconductor device. Also, when the semiconductor device is of a flip-chip type, a metal bump is bonded and connected to each of the electrode pads on the semiconductor device. In either event, each of the electrode pads is subjected to physical stresses when bonding and connecting either the gold wire or the metal bump thereto, and thus cracks may be produced in the insulating interlayer structures included in the multi-layered wiring arrangement.
In order to prevent the production of the cracks in the insulating interlayer structures, it has been already proposed that reinforcing metal patterns be incorporated in the multi-layered wiring arrangement below each of the electrode pads, as disclosed in JP-A-2003-031611.
On the other hand, with the recent advance of miniaturization of semiconductor devices, a signal-transmission path included in the metal wiring layout patterns formed becomes narrower. Of course, the narrower the signal-transmission path, the larger resistance of the signal-transmission path, resulting in delay of signal transmission in the signal-transmission path.
Conventionally, in general, although the metal wiring layout patterns are made of aluminum, there is a recent trend toward use of copper, exhibiting a smaller specific resistance than that of aluminum, for the metal wiring layout pattern, whereby the signal transmission can be facilitated in the signal-transmission paths of the metal wiring layout pattern.
Also, the signal-transmission paths included in the metal wiring layout pattern become closer to each other for the miniaturization of semiconductor devices, and thus a parasitic capacitance is produced between adjacent signal-transmission paths because the silicon dioxide layer serves as a dielectric therebetween. Of course, the production of the parasitic capacitance results in delay of signal transmission in the signal-transmission paths. In short, the miniaturization of the semiconductor devices has advanced to a degree in which a magnitude of a dielectric constant of the silicon dioxide layer cannot be neglected.
Thus, in the production of the semiconductor devices, it has been proposed that a low-k material having a smaller dielectric constant than that of silicon dioxide (SiO2) be used to form the insulating interlayer structures of the multi-layered wiring arrangement, to thereby suppress the production of the parasitic capacitance. Note, for the low-k material, SiOCH is representatively used.
In general, since it is difficult to minutely process a copper layer by using a dry etching process to thereby produce a copper wiring layout pattern, a damascene process is used for the production of the minute copper wiring layout pattern.
As well known, a low-k insulating layer made of the low-k material exhibits a lower density than that of a silicon dioxide layer, and thus the physical strength of the low-k insulating layer is inferior to that of the silicon dioxide layer. Also, the low-k insulating layer exhibits an inferior adhesion property with respect to another insulating layer, such as a silicon dioxide layer or the like.
Accordingly, in the production of the multi-layered wiring arrangement, when an insulating interlayer structure is constituted by using the low-k material, cracks are liable to be produced in a low-k insulating layer due to thermal stresses and/or physical stresses. Also, in the aforesaid damascene process, a chemical and mechanical polishing (CMP) process is involved to polish a copper layer for producing a copper wiring layout pattern, and thus peeling is liable to occur in the low-k insulting layer due to physical stresses produced in the insulating interlayer structures during the CMP process.